OPSILIN's IP platform currently comprises two core digital controller products, developed as configurable, reusable IP blocks:

1. LPDDR5X/LPDDR6 Memory Controller IP — Enables high-bandwidth, low-power external DDR memory access for AI accelerator SoCs, high-performance RISC-V SoCs, edge AI processors, industrial and IoT SoCs, and other domain-specific silicon. Key architectural blocks include an AXI4/AXI5-L host interface, a v5.2/6 DFI (DDR PHY Interface), an APB/AXI5-L configuration interface, address mapping, DDR maintenance and RAS (Reliability, Availability, Serviceability) support, a command queue, and an efficient scheduler. The controller is designed with a clean PHY-facing interface, enabling future integration with third-party or partner PHY IP.

2. UCIe Digital Controller IP — Enables die-to-die connectivity for next-generation chiplet-based systems, aligned with the industry's shift from monolithic SoCs to heterogeneous, modular silicon. The first version implements UCIe protocol and adapter layer functionality up to the RDI (Raw Die-to-Die Interface) boundary, focused on streaming-mode data movement, with key blocks including an AXI4 streaming interface, protocol bridge (AXI-to-FDI), and UCIe adapter layer (FDI-to-RDI).